Wafer Level Package (WLP) is a modified and enhanced CSP based on BGA technology. Some people also refer to WLP as chip level Chip Size Package (WLP-CSP). Wafer-level packaging technology takes wafers as processing objects, packages, ages and tests many chips on wafers at the same time, and finally cuts them into a single device, which can be mounted directly to the substrate or printed circuit board. It reduces the package size to the size of the IC chip, and the production cost is greatly reduced.

Advantages of wafer-level packaging:

• Packaging processing efficiency is high, it is manufactured in the form of a mass production process;
• It has the advantages of flip chip package, that is, light, thin, short and small;
• The cost of wafer level packaging production facilities is low, which can make full use of wafer manufacturing equipment, and there is no need to invest in another packaging production line;
• Wafer-level packaging from chip manufacturing, packaging to the entire process of product delivery to the user, the intermediate links are greatly reduced, the cycle is shortened a lot, which will lead to cost reduction;
• The cost of wafer-level packaging is closely related to the number of chips on each wafer, and the more chips on the wafer, the lower the cost of wafer-level packaging. Wafer-level packages are the smallest, low-cost packages.
  

The advantages of wafer-level packaging technology make it receive great attention and get great development and wide application quickly. In portable products such as mobile phones, wafer-level packaged EPROM, IPD (integrated passive devices), analog chips and other devices have been widely used. Wafer-level packaging technology has been widely used in flash memory, EEPROM, high-speed DRAM, SRAM, LCD drivers, RF devices, logic devices, power/battery management devices, and simulator components (regulators, temperature sensors, controllers, operational amplifiers, power amplifiers).

Key processes of WL-CSP:

1. Thin film redistribution technology

In this process, BCB/PI is used as the redistributed medium layer, Cu is used as the redistributed wire metal, UBM is deposited by sputtering method, and solder paste is deposited and reflow by screen printing method.

Souce：Baidu

The first Polymer Layer is coated to strengthen the Passivation layer of the chip and act as a stress buffer. The most common polymer film available today is photosensitive Polyimide, or PI, which is a negative adhesive.

• BCB (Benzocyclobutene) was used as the rewired polymer film in the early WLP, but it was limited by low mechanical properties (low elongation at break and tensile strength) and high process cost (adhesion layer adhesion promoter required). Prompted material manufacturers to develop PI and PBO (Polubenzoxazole).
• The purpose of the rewiring layer (RDL) is to rearrange the position of the aluminum welding zone of the chip, so that the new welding zone meets the requirements of the minimum spacing of the solder ball, and the new welding zone is arranged according to the array.
• A common RDL material is plated Cu with a base of titanium and copper Sputtered layer (Sputtered Ti/Cu).
• A second layer of Polymer is applied to flatten the surface of the disc and protect the RDL layer. The position of the second Polymer after photolithography opens the new welding area.
• The final metal layer is UBM (Under Bump Metalization), which is made using the same process as RDL.
• Plant balls. In line with the requirements of lead-free environmental protection, the solder balls currently used in WLP are all solder copper alloys. The solder ball is typically 250µm in diameter. In order to ensure that the solder paste and solder ball are accurately positioned on the corresponding UBM, a mask is used. The solder ball is placed on the UBM through the opening of the mask, and finally the silicon wafer after planting the ball is pushed into the reflux furnace to reflux, and the solder ball is melted into the UBM by reflux to form a good infiltration bond.

2. Solder bump production technology

Bump making is the key process of wafer level packaging process, which is to form bump on the aluminum electrode in the press welding area of wafer. There are many methods commonly used in wafer level package convex manufacturing process, each method has its own advantages and disadvantages, and is suitable for different process requirements. In order to make the wafer level packaging technology more widely used, it is very important to select a suitable convex point manufacturing process. In wafer bump fabrication, metal deposition accounts for more than 50% of the total cost. The most common metal deposition steps in wafer bump manufacturing are the deposition of the metallized layer (UBM) under the bump and the deposition of the bump itself, which are generally achieved by the electroplating process.

The projection preparation process requires that the projection base metal (UBM) be covered with new welding material

The following figure shows a typical wafer bump production process. The UBM layer is first fabricated on the wafer. Thick glue is then deposited and exposed to form a template for plating solder. After plating, the photoresist is removed and the exposed UBM layer is etched away. The final process is the re-flow to form the solder ball.

Electroplating technology can achieve very narrow convex pitch and maintain high yield. And the application range of this technology is also very wide, can produce different sizes, pitch and geometric shape of the convex point, electroplating technology has been more and more widely used in the wafer convex point production has become a valuable solution.

Research progress in wafer-level packaging

• Standard WLP (fan-in WLP) is to package the chip before the wafer is sliced, and then slice and divide it, and the package size after completion is the same as the size of the chip.
• The diffused WLP (fan-out WLP) developed in recent years is based on wafer reconstruction technology, where the chip is rearranged on an artificial wafer and then packaged in a similar step to the standard WLP process, resulting in a package area larger than the chip area.

Different WLP structures

• The first is the ball on I/O structure, as shown in Figure (a). This process is similar to the typical inversion process. The solder ball is directly connected to the aluminum disk through the metal layer under the solder joint (a) or to the Si chip through the redistribution layer (RDL) (Figure (a)2).
  Normally, this structure is limited to a 6x6 array structure with a solder ball spacing of 0.5mm to meet the requirements of thermal cycle reliability.

• The second structure is shown in Figure (b), in which the solder ball is placed on the RDL layer and connected to the Si chip by two polymer dielectric layers, without the metal layer under the solder joint. Two polymer layers serve as passivation and rewiring layers. This structure is different from the first, although both structures have rewiring layers. As shown in Figure b, the polymer dielectric film layer is placed on the welding ball and the silicon substrate. This polymer layer can act as a buffer layer to reduce the thermal mechanical stress caused by the thermal mismatch between PCB and silicon due to temperature changes. This WLP structure can be extended to a 12x12 ball array with a spacing of 0.5mm.

• The third WLP structure, shown in Figure (c), adds a UBM layer on top of Figure (b). Due to the addition of this UBM layer, manufacturing costs are correspondingly increased. This UBM can improve the thermodynamic performance slightly.

• The fourth WLP structure, as shown in Figure (d), adopts a copper column structure, which is first electroplated with copper column and then sealed with epoxy resin.

WLP（fan-out WLP）

• Diffuse WLP uses wafer reconstruction technology. The process is shown in the following figure: First, a piece of tape is affixed to a laminated board. The carrier board is usually an artificial wafer, and the tape on the carrier board acts as a fixed chip position and protects the active surface of the chip. Then the well tested chip (KGD) is re-pasted to a carrier board facing down. The distance between the chips determines the size of the diffusion area during packaging, which can be freely controlled according to needs. Then the chip and the gap between the chips are covered and filled with molding plastic, and the carrier plate and tape are separated from the system, and the carrier plate can be reused; Finally, RDL and ball process steps can be carried out.

• A typical application of diffuse WLP is embedded wafer level ball grid array (eWLB).

The benefits of fan-out WLP packages

1. Smaller and thinner package
2. Multi-chip, IPD or passively integrated SIP solutions
3. Low-cost path with batch processing and simple supply chain
4. Scaleable technology leads to larger panel production - lower cost
5. Flexible 3D package path - on top of any array graphics
6. Good electrical and thermal performance
7. High frequency application
8. Extremely advantageous for RF and mixed signals due to low parasitic parameters compared to any laminated based package
9. High density cabling is easy to achieve in RDL

Application of WLP in 3D laminated packaging

• 3D laminated packaging has great advantages in shortening the length of the interconnect, reducing the form factor, and improving the electrical performance. The application of WLP in 3D packaging adopts flip bump and RDL technology, which can realize wafer level interconnection and improve interconnection density.
  The application of TSV technology in WLP-3D package is the key to realize vertical interconnection. It has the advantages of improving integration, reducing interconnection length, improving signal speed, reducing power consumption, etc., and can also realize multi-function integrated package such as memory, special IC, processor in one package.

• TSV is usually filled with Cu. Due to the different coefficient of thermal expansion of Cu and Si, there are problems of thermal-mechanical reliability in the thermal cycle of TSV.
  For high-density TSV, the through hole should be completely filled. In order to improve reliability, save process time and reduce costs, the medium density TSV is not completely filled with copper, but is electrochemically deposited and electroplated with a thin layer of copper lining to ensure electrical connection, and the remaining part is filled with polymer.
  
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• There are two main trends in the development of WLP. One is to reduce the process cost and shorten the process time by reducing the number of layers of WLP, mainly for products with less I/O and small chip size. Its structure is derived from the above 4M structure, which is mainly divided into 3M and 2M structures.
  Another development direction is to improve the performance and reliability of WLP through the application of some new materials. It is mainly for products with many I/O and large chip size. For example, as mentioned above, although the solder ball of tin silver copper alloy meets the requirements of lead-free environmental protection, the temperature of reflow welding will be higher than that of tin lead solder ball, and the thermal stress of the product is relatively large. The use of a new material, tin-silver-cop-bismuth alloy solder ball, due to its lower melting point and better wetting ability, will improve the thermal stress mismatch problem in the WLP loading process.
  

Thermal stress mismatch problem in WLP loading process

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